Non-volatile memory devices and methods of forming the same

ABSTRACT

A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.

RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35U.S.C §119 of Korean Patent Application 2007-0071237 filed on Jul. 16,2007, the entirety of which is hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and methods offorming the same. More specifically, the present invention is directedto non-volatile memory devices and methods of forming the same.

BACKGROUND OF THE INVENTION

Non-volatile memory devices retain their stored data even when theirpower supplies are interrupted. Flash memory devices are well known asrepresentative non-volatile memory devices. A flash memory deviceincludes a unit cell with an electrically isolated charge storingelement. A threshold voltage of a flash memory cell can be regulated bystoring charges in the charge storing element or ejecting charges fromthe charge storing element, so as to store predetermined logical data inthe flash memory cell and allow the stored logical data to be readtherefrom. A flash memory device can write and/or erase dataelectrically.

Conventionally, a flash memory device requires low operation voltages(e.g. a program voltage, an erase voltage and/or a verify voltage,etc.). With the rise of operation voltages such as a program voltageand/or an erase voltage, characteristics of an oxide layer that isformed to surround a charge storing element may become degraded andresult in erroneous operation, such as loss of the data stored in thecharge storing element.

In addition, flash memory devices are required to have long-term dataretention characteristics. However, charges stored in the charge storingelement may leak through an oxide layer (e.g., an oxide layer interposedbetween the charge storing element and a semiconductor substrate). Thus,stored data may be lost over time and thereby cause malfunction of theflash memory device.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention are directed tonon-volatile memory devices and methods of forming the same. In anembodiment thereof, the non-volatile memory device may include: adielectric layer including an oxide layer on a substrate, the dielectriclayer including at least two regions therein that each extend across atleast a major extent of the dielectric layer and have significantlyhigher nitrogen concentration relative to other regions of thedielectric layer; a charge storage layer on the dielectric layer; ablocking insulating layer on the charge storage layer; and a gateelectrode on the blocking insulating layer.

In another embodiment, the method may include: forming a dielectriclayer including a nitride layer on a substrate; transforming at least aportion of the nitride layer extending across at least a major lateralextent of the dielectric layer to include added oxygen; forming a chargestorage layer on the dielectric layer; forming a blocking insulatinglayer on the charge storage layer; and forming a gate electrode on theblocking insulating layer.

In yet another embodiment, the method may include: forming a dielectriclayer on a substrate; reacting at least a major portion of free bondsremaining in the dielectric layer with each other; forming a chargestorage layer on the dielectric layer; forming a blocking insulatinglayer on the charge storage layer; and forming a gate electrode on theblocking insulating layer.

In still another embodiment, the method may include: forming an oxidelayer on a substrate; forming a nitride layer on the oxide layer;oxidizing at least a portion of the nitride layer; forming a chargestorage layer on the oxidized nitride layer; forming a blockinginsulating layer on the charge storage layer; and forming a gateelectrode on the blocking insulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 5 are cross-sectional views illustrating methods offorming a non-volatile memory device according to some embodiments ofthe present invention.

FIG. 6 is a flowchart illustrating methods of forming a dielectric layerin a non-volatile memory device according to some embodiments of thepresent invention.

FIG. 7 is a cross-sectional view illustrating other methods of forming anon-volatile memory device according to some embodiments of the presentinvention.

FIG. 8 is a cross-sectional view of a non-volatile memory deviceaccording to some embodiments of the present invention.

FIG. 9 is a graph illustrating concentrations of nitrogen in adielectric layer of a non-volatile memory device according to exemplaryembodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichembodiments of the invention are shown. This invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein. Rather, these embodiments areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the invention to those skilled in the art.Like numbers refer to like elements throughout.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”“comprising,” “includes” and/or “including” when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

It will be understood that when an element such as a film, region orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present. Itwill also be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or“horizontal” or “vertical” may be used herein to describe a relationshipof one element, film or region to another element, film or region asillustrated in the figures. It will be understood that these terms areintended to encompass different orientations of the device in additionto the orientation depicted in the figures.

Embodiments of the invention are described herein with reference tocross-section illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of the invention.The thickness of films and regions in the drawings may be exaggeratedfor clarity. Additionally, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, embodiments of theinvention should not be construed as limited to the particular shapes ofregions illustrated herein but are to include deviations in shapes thatresult, for example, from manufacturing. For example, an implantedregion illustrated as a rectangle will, typically, have rounded orcurved features and/or a gradient of implant concentration at its edgesrather than a discrete change from implanted to non-implanted region.Likewise, a buried region formed by implantation may result in someimplantation in the region between the buried region and the surfacethrough which the implantation takes place. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the actual shape of a region of a device andare not intended to limit the scope of the invention.

FIGS. 1 through 5 are cross-sectional views illustrating methods offorming a non-volatile memory device according to some embodiments ofthe present invention. FIG. 6 is a flowchart illustrating methods offorming a dielectric layer in a non-volatile memory device according tosome embodiments of the present invention, and FIG. 7 is across-sectional view illustrating other methods of forming anon-volatile memory device according to some embodiment of the presentinvention.

Referring to FIGS. 1 through 6, some methods of forming a non-volatilememory device include forming a dielectric layer (515 of FIG. 3) on asemiconductor substrate 500, which will be described below in detailwith reference to the flowchart of FIG. 6 and the cross-sectional viewsof FIGS. 1 through 3.

An oxide layer 505 is formed on the substrate 500 (S550). The oxidelayer 505 may be formed as thermal oxide by a thermal oxidation processcarried out on the substrate 500. Alternatively, the oxide layer 505 maybe formed by depositing oxide, such as by a chemical vapor deposition(CVD), on the substrate 500. A device isolation layer (not shown) may beformed in the substrate 500 to define an active region (not shown). Theactive region may be defined in a portion of the substrate 500 that issurrounded by the device isolation layer. The oxide layer 505 may berestrictively formed on a defined portion of a top surface of the activeregion, or it may be formed on the entire surface of the substrate 500.The oxide layer 505 may be formed before or after the formation of thedevice isolation layer.

After the oxide layer 505 is formed (S550), it may be subjected to anitridation treatment (S555) in which nitrogen atoms are introduced intothe oxide layer 505. The introduced nitrogen atoms may accumulate at afirst interface region 600 between the oxide layer 505 and the substrate500, and result in a significant nitrogen concentration (e.g.,substantially more nitrogen concentration) at the first interface region600 relative to other areas thereof. The first interface region 600having the significant nitrogen concentration is hereinafter referred toas a first nitrogen accumulation region. The first nitrogen accumulationregion may have a nitrogen concentration in a range of, for example, 1to 20 percent per volume. However, the nitrogen concentration of thefirst nitrogen accumulation region is not limited to any particularrange.

Free bonds (e.g., free dangling bonds) may be created at the firstinterface region 600 by the different materials of the oxide layer 505and the substrate 500 contacting each other. The term free bonds is usedherein to refer to an unsaturated bonding state, and may be created whenatoms in the first interface region 600 are not bonded completely to oneanother. The free bonds of the first boundary region 600 can besignificantly reduced by the nitridation treatment (S555) introducingnitrogen atoms into the oxide layer 505. In particular, the nitrogenatoms of the first nitrogen accumulation region, formed by thenitridation treatment, can bond to at least some of the free bonds ofthe first interface region 600, and thereby eliminate those free bonds.

A relatively small amount of bulk free bonds may exist in the oxidelayer 505, and can bond to the nitrogen atoms that are introduced by thenitridation treatment (S555). Thus, bulk free bonds in the oxide layer505 may also be reduced by than the nitridation treatment (S555).

The nitridation treatment may be performed at least in part by a thermalnitridation process, a plasma nitridation process, and/or a radicalnitridation process. The radical nitridation process is a nitridationprocess that uses a process gas with a sufficiently excited radicalstate. The plasma nitridation process and/or the radical nitridationprocess may use heat energy auxiliary. The process gas of thenitridation treatment may include at least one selected from the groupconsisting of nitrogen (N₂) gas, nitrogen oxide (NO) gas, dinitrogenoxide (N₂O) gas, and ammonia (NH₃) gas.

Referring to FIGS. 2 and 6, a nitride layer 510 is formed on the oxidelayer 505 (S560). The nitride layer 510 may be formed with, for example,silicon nitride. The nitride layer 510 may be formed by chemical vapordeposition (CVD). The nitride layer 510 may include free bonds, whichmay be created when atoms of the nitride layer 510 are not completelybonded to other atoms. The nitride layer 510 can be formed directly onthe oxide layer 505, which may result in the formation of a secondinterface region 610 between the nitride layer 510 and the oxide layer505.

Referring to FIGS. 3 and 6, an oxidation process is performed to oxidizethe nitride layer 510 (S565). The oxidized nitride layer 510 a and theoxide layer 505 can form a dielectric layer 515. During an eraseoperation and/or a program operation of a non-volatile memory deviceincluding the exemplary structure, charges can tunnel through thedielectric layer 515.

The oxidation process (S565) transforms at least a portion of thenitride layer 510 extending across at least a major lateral extent ofthe dielectric layer to contain added oxygen. The oxygen added to thenitride layer 510 by the oxidation process (S565) can reduce free bondsin the oxidized nitride layer 510 a. In particular, the oxidationprocess (S565) reacts at least some of the free bonds in the nitridelayer 510 with each other and, thereby, reduces the free bonds in theoxidized nitride layer 510 a. Oxygen atoms supplied by the oxidationprocess (S565) can replace some nitrogen atoms and the nitride layer510. In the course of the substitution, at least some of the free bondsin the nitride layer 510 may react with each other and, thereby, beeliminated. As a result, the amount of free bonds in the oxidizednitride layer 510 a can be substantially reduced relative to the amountof free bonds in the nitride layer 510.

At least a portion of the oxidized nitride layer 510 may be formed fromoxide. As previously explained, oxygen atoms can replace some nitrogenatoms of the nitride layer 510, and thereby form at least a portion ofthe oxidized nitride layer 510 a from oxide. Following the oxidationprocess (S565), the nitrogen atoms replaced by the oxygen atoms mayprimarily accumulate in a defined region of the dielectric layer 515.Alternatively, the replaced nitrogen atoms may be released from thedielectric layer 515 by being converted to gaseous form. The gaseousnitrogen atoms can be exhausted from a process chamber in which theoxidation process is performed.

As illustrated in FIG. 3, the nitride layer 510 may be fully oxidized bythe oxidation process, such as by oxidizing the entire nitride layer 510through the oxidation process. Thus, a substantial portion or all of theoxidized nitride layer 510 a may be formed of oxide, and a substantialportion or all of the dielectric layer 515 may be formed of oxide. Atthis point, a part of the nitrogen atoms replaced by the oxygen atomsmay accumulate in a predetermined region of the dielectric layer 515 toform a region having a significant nitrogen concentration in thedielectric layer 515 relative to other areas thereof. The region of thedielectric layer 515 having a significant nitrogen concentration ishereinafter referred to as a second nitrogen accumulation region. Thesecond nitrogen accumulation region may be formed along the secondinterface region 610. The second nitrogen accumulation region may have anitrogen concentration in a range of, for example, 1 to 15 percent pervolume. However, the nitrogen concentration of the second nitrogenaccumulation region is not limited to any particular range.

A relatively small amount of bulk free bonds may also exist in theoxidized nitride layer 510 a. At least some of the bulk free bonds inthe oxidized nitride layer 510 a may bond to the substituted nitrogenatoms, which may substantially reduce or eliminate the presence of bulkfree bonds in the oxidized nitride layer 510 a.

As illustrated in FIG. 7, the nitride layer 510 may be partiallyoxidized, such as along an upper portion thereof, by the oxidationprocess. Accordingly, a dielectric layer 515′ can be formed thatincludes an oxide layer 505, a residual nitride layer 510′, and anoxidized nitride layer 510 a, which are stacked in the listed order.Free bonds can be significantly reduced in the oxidized portion of thenitride layer 510.

For the convenience of description, a process of fully oxidizing thenitride layer 510 is hereinafter referred to as a full oxidation processand a process of partially oxidizing the nitride layer 510 ishereinafter referred to as a partial oxidation process.

Returning to FIG. 6, some methods of forming a dielectric layeraccording to embodiments of the present invention may include repeatedlyperforming the steps S560 and S565 at least two times. The repetitivelyperformed oxidation step S565 may each be the full oxidation process orthe partial oxidation process, or, alternatively, some of therepetitively performed oxidation steps S565 may be the full oxidationprocess and some others may be the partial oxidation process.

As described above, in the case where the nitride layer 510 is fullyoxidized, the dielectric layer 515 includes at least the first andsecond nitrogen accumulation regions. When the steps S560 and S565 arerepeatedly performed at least two times and at least one of therepeatedly performed steps S565 is the full oxidation process, thedielectric layer can include at least three regions each having asubstantially high nitrogen concentration. The dielectric layer 515 mayhave a sufficient thickness, such as greater than 25 angstroms, toinhibit/prevent direct tunneling of charges therethrough duringoperation of the non-volatile memory device formed therewith.

The oxidation process can be carried out using a process gas containingoxygen. For example, the oxidation process may use a process gascontaining at least one selected from the group consisting of oxygen(O₂) gas, ozone (O₃) gas, and vapor (H₂O). The oxidation process may becarried out as a dry oxidation process, a wet oxidation process, aradical oxidation process, a plasma oxidation process, and/or anoxidation process using hydrogen chloride.

Returning to FIG. 4, a charge storage layer 520 is formed on thedielectric layer 515. A blocking insulating layer 525 is formed on thecharge storage layer 520. A gate conductive layer 530 is formed on theblocking insulating layer 525. The dielectric layer 515 can be replacedwith a dielectric layer 515′ shown in FIG. 7. Furthermore, thedielectric layer 515 can be replaced with any one or more of thedielectric layers described herein.

The charge storage layer 520 can be formed from a material that isconfigured to store charges. Further, the charge storage layer 520 mayinclude trap sites to store charges. The charge storage layer 520 mayinclude a single layer or multiple layers. For example, the chargestorage layer 520 may include at least one material selected from thegroup consisting of silicon nitride, silicon oxynitride, a high-kdielectric (e.g., hafnium aluminate, hafnium silicate, etc.) having ahigher dielectric constant than silicon oxide, and an insulatingmaterial where dots (described below) can be uniformly distributed inthe insulating material. The hafnium aluminate may be HfSiO or HfSiON.The dots may be formed from silicon, silicon germanium, and/or metal,and can be defined in relatively small spaced apart regions in theinsulating material. The charge storage layer 520 may include at leastone insulating layer having the same as or higher dielectric constantthan the blocking insulating layer 525.

Alternatively, the charge storage layer 520 may be formed of dopedsilicon or undoped silicon. In this case, the dielectric layer 515 andthe charge storage layer 520 may be formed on the active region (notshown) to be self-aligned to the active region. The blocking insulatinglayer 525 may be formed after the formation of the device isolationlayer (not shown).

The blocking insulating layer 525 may be a single layer or multiplelayers. The blocking insulating layer 525 includes at least oneinsulating layer having a higher dielectric constant than the dielectriclayer 515. In particular, the blocking insulating layer 525 may includeat least one insulating layer having a higher dielectric constant than ahighest dielectric constant portion (e.g., a highest dielectric constantof a major portion) of the dielectric layer 515. The first and secondnitrogen accumulation regions may have a higher dielectric constant thana substantially low nitrogen concentration portion of the dielectriclayer 515. In this case, the blocking insulating layer 525 may includeat least one insulating layer having a higher dielectric constant thanthe first and second nitrogen accumulation regions.

Referring to FIG. 7, when the dielectric layer 515′ includes a residualinsulating layer 510′, the blocking insulating layer 525 may include atleast one insulating layer having a higher dielectric constant than theresidual nitride layer 510′. For example, the blocking insulating layer525 may include an insulative metal oxide (e.g., hafnium oxide, aluminumoxide, etc.) having a high-k dielectric constant, hafnium aluminate(e.g., HfAlO or HfAlON), and/or hafnium silicate (e.g., HfSiO orHfSiON).

When both the charge storage layer 520 and the blocking insulating layer525 include hafnium aluminate or hafnium silicate, a hafnium ratio ofthe charge storage layer 520 (e.g., concentration of hafnium relative toother material(s) in the charge storage layer 520) may be higher thanthat of the blocking insulating layer 525. Consequently, a trap densityof the charge storage layer 520 may be increased and the insulatingcharacteristics of the blocking insulating layer 525 may be enhanced.

The gate conductive layer 530 may be a single layer or multiple layers.The gate conductive layer 530 may include doped silicon, metal,conductive metal nitride, a metal containing material, and/or metalsilicide. At least a portion of the gate conductive layer 530 contactingthe blocking insulating layer 525 can be formed from a conductivematerial having a high work function to decrease/prevent chargetunneling through the blocking insulating layer 525. In particular, atleast a portion of the gate conductive layer 530 contacting the blockinginsulating layer 525 may be formed from a conductive material having awork function that is equal to or higher than 4.0 eV. For example, atleast a portion of the gate conductive layer 530 contacting the blockinginsulating layer 525 may include P-type silicon, Ti, TiN, TaN, TaTi,TaSiN, Ta, W, Hf, HfN, Nb, Mo, RuO₂, RuO, MoN, WN, WSi, NiSi, Ti₃Al,Ti₂AlN, Pd, Ir, Pt, Co, Cr, CoSi, NiSi, and/or AlSi.

Referring to FIG. 5, the gate conductive layer 530 is patterned to forma gate electrode 530 a. The gate electrode 530 crosses over the activeregion. When the charge storage layer 520 is formed of doped silicon orundoped silicon, the gate conductive layer 530, the blocking insulatinglayer 525, and the charge storage layer 520 may be successively etched.Thus, an electrically isolated charge storage layer 520 can be formedbetween the gate electrode 530 a and the substrate 500.

Alternatively, when the charge storage layer 520 is formed of theabove-mentioned insulating material, the gate conductive layer 530 maybe etched using the blocking insulating layer 525 as an etch-stop layerto form the gate electrode 530 a. Alternatively or additionally, thegate electrode 530 a may be formed by successively etching the gateconductive layer 530, the blocking insulating layer 525, and the chargestorage layer 520.

A source region 535 s and a drain region 535 d, shown in FIG. 8, areformed in the substrate 500 adjacent to opposite sides of the gateelectrode 530 a. The source and drain regions 535 s and 535 d can beformed by introducing dopant ions into the substrate 500. Alternatively,the source and drain regions 535 s and 535 d may be an inversion layerformed by inverting the surface of the substrate 500, such as by forminga material layer on the source and drain regions 535 s and 535 d toinvert the surface of the substrate 500.

Thus, according to some exemplary methods of forming a non-volatilememory device, at least a portion of the nitride layer 510 is oxidizedduring the oxidation process to reduce free bonds in the nitride layer510. Free bonds in the dielectric layer 515 or 515′ between the chargestorage layer 520 and the substrate 500 may thereby be reduced/minimizedto enhance data retention properties and/or durability of the resultingnon-volatile memory device.

If the free bonds in the dielectric layer 515 or 515′ were not reducedas described herein, the charges stored in the charge storage layer 520could more readily leak therefrom to the substrate 500 by tunnelingusing the free bonds, which would degrade the data retention propertiesof the non-volatile memory device. Moreover, if the free bonds in thedielectric layer 515 or 515′ were not reduced as described herein, thenduring an erase operation and/or a program operation of the non-volatilememory device, tunneling charges may be trapped by the free bonds, whichmay change the program threshold voltage and erase threshold voltageover time with the repetition of the program and erase operations of thenon-volatile memory device, and may therefore degrade the durability ofthe non-volatile memory device. However, as described above inaccordance with various embodiments, the nitride layer 510 including alarge amount of free bonds can be oxidized to reduce/minimize the freebonds in the dielectric layer 515. Thus, the data retention propertiesand/or the durability of the non-volatile memory device may be enhanced.

Following the formation of the oxide layer 505, a nitridation treatmentcan be performed to form a first nitrogen accumulation region at thefirst interface region 600. Nitrogen atoms of the first nitrogenaccumulation region can bond to the free bonds of the first interfaceregion 600 to suppress the leakage of charges stored in the chargestorage layer 520 and prevent the charges from being trapped to suchfree bonds. Thus, the data retention properties and/or the durability ofthe non-volatile memory device may be enhanced.

Moreover, the nitrogen accumulation regions have a narrower energy bandgap than portions formed of oxide in the dielectric layer 515 (e.g., theoxide layer 505 below the second nitrogen accumulation region and theoxidized nitride layer 510 a on the second nitrogen accumulationregion), which may enhance the efficiency of an erase operation in whichthe charges stored in the charge storage layer 520 are ejected to thesubstrate 500. Further, as illustrated in FIG. 7, when the dielectriclayer 515′ includes the residual nitride layer 510′, an energy band gapof the residual nitride layer 510′ is also narrower than that ofportions formed of oxide in the dielectric layer 515′, which may enhancethe efficiency of an erase operation of the non-volatile memory device.

The blocking insulating layer 525 includes at least one insulating layerhaving a higher dielectric constant than a highest dielectric constantportion (e.g., a highest dielectric constant of a major portion) of thedielectric layer 515. Thus, a minimum field in the dielectric layer 515is stronger than that in the blocking insulating layer 525 when avoltage is applied to the gate electrode 530 a and to the substrate 500to generate a potential difference therebetween. Therefore, the amountof charges migrating through the dielectric layer 515 increases whilethe amount of charges migrating through the blocking insulating layer525 decreases. As a result, a difference between limit values of aprogram threshold voltage and an erase threshold voltage may increaseand erase and program times may be reduced. Moreover, the data retentionproperty of the non-volatile memory device may be enhanced. Due to theabove effects, the non-volatile memory device according to variousembodiments may operate as a multi-bit non-volatile memory device.

At least a portion of the gate conductive layer 530 contacting theblocking insulating layer 525 can have a work function that is equal toor higher than 4.0 eV. Accordingly, charge tunneling through theblocking insulating layer 525 may decrease, which can reduce programand/or erase times of a non-volatile memory device and increase adifference between limit values of a program threshold voltage and anerase threshold voltage.

A non-volatile memory device according to some embodiments of thepresent invention will now be further described below with reference toFIGS. 8 and 9.

FIG. 8 is a cross-sectional view of a non-volatile memory deviceaccording to some embodiments of the present invention, and FIG. 9 is agraph illustrating a concentration of nitrogen in a dielectric layer ofa non-volatile memory device according to an exemplary embodiment of thepresent invention. In FIG. 9, the x-axis represents positions and they-axis represents a nitrogen concentration depending on the position.

Referring to FIGS. 8 and 9, a source region 535 s and a drain region 535d are in a substrate 500 and are spaced apart from each other. Adielectric layer 515, a charge storage layer 520, a blocking insulatinglayer 525, and a gate electrode 530 a are sequentially stacked on achannel region between the source region 535 s and the drain region 535d.

The dielectric layer 515 includes an oxide layer. More specifically, thedielectric layer 515 includes an oxide layer 505 and an oxidized nitridelayer 510 a which are stacked in the order listed. The entirety of adeposited nitride layer may be fully oxidized to form the oxidizednitride layer 510 a. Accordingly, the dielectric layer 515 may include acombined oxide layer that includes the oxide layer 505 and the oxidizednitride layer 510 a. The dielectric layer 515 includes at least tworegions having a substantially high nitrogen concentration, which ishereinafter referred to as nitrogen accumulation regions 620 and 630.

The first nitrogen accumulation region 620 is disposed at a firstinterface region 600 between the substrate 500 and the combined oxidelayer included in the dielectric layer 515. The second nitrogenaccumulation region 630 is disposed in the combined oxide layer includedin the dielectric layer 515. The second nitrogen accumulation region 630may be disposed at a second interface region 610 between the oxide layer505 and the oxidized nitride layer 510 a. A nitrogen concentration ofthe first nitrogen accumulation region 620 may be different from that ofthe second nitrogen accumulation region 630. In particular, the nitrogenconcentration of the first nitrogen accumulation region 620 may behigher than that of the second nitrogen accumulation region 630. Forexample, the first nitrogen accumulation region 620 may have a nitrogenconcentration in a range of 1 to 15 percent per volume, and the secondnitrogen accumulation region 630 may have a nitrogen concentration in arange of 1 to 20 percent per volume. More generally, the first andsecond nitrogen accumulation regions 620 and 630 can have differentnitrogen concentrations from each other.

As described above, the charge storage layer 520 includes a material tostore charges. For example, the charge storage layer 520 may include atleast one insulating layer having trap sites to store charges. In thiscase, the gate electrode 530 a, the blocking insulating layer 525, andthe charge storage layer 520 may have sidewalls that are aligned to eachother. Alternatively, the blocking insulating layer 525 and the chargestorage layer 520 may laterally extend so as to essentially cover theentirety of the substrate 500.

The charge storage layer 520 may be formed from doped silicon or undopedsilicon. In this case, the charge storage layer 520 may have a patternedshape so as to be electrically isolated from other charge storage layersand/or features of the non-volatile memory device. For example, the gateelectrode 530 a, the blocking insulating layer 525, and the chargestorage layer 520 can include sidewalls that are aligned to each otheras illustrated in FIG. 8.

When a voltage is applied between the gate electrode 530 a and thesubstrate 500 to generate a potential difference therebetween, a minimumfield in the dielectric layer 515 is stronger than that in the blockinginsulating layer 525. Since an electric field applied to an insulatinglayer is inversely proportion to its dielectric constant, the blockinginsulating layer 525 includes at least one insulating layer having ahigher dielectric constant than a highest dielectric constant portion(e.g., a highest dielectric constant of at least a major portion) of thedielectric layer 515. The blocking insulating layer 525 and the chargestorage layer 520 can be formed from the same materials, such asdescribed above with reference to FIG. 4 and, accordingly, furtherdescription thereof is omitted.

The gate electrode 530 a is made of a conductive material. At least aportion of the gate electrode 530 a contacting the blocking insulatinglayer 525 can be formed from a conductive material having a high workfunction of at least 4.0 eV. Therefore, it can be possible to decreasetunneling of charges migrating from the gate electrode 530 a to thecharge storage layer 520 through the blocking insulating layer 525. As aresult, program operation efficiency and/or erase operation efficiencyof a non-volatile memory device may be enhanced.

The gate electrode 530 a can be made of the same material as describedabove with regard to FIG. 4, so further description thereof is omitted.

According to various embodiments of the foregoing non-volatile memorydevice, the dielectric layer 515 between the charge storage layer 520and the substrate 500 can include the combined oxide layer in which freebonds are reduced/minimized and can have at least two nitrogenaccumulation regions 620 and 630. Nitrogen atoms of the first nitrogenaccumulation region 620 are bonded to the free bonds of the firstinterface region 600, thereby minimizing the free bonds of the firstinterface. The second nitrogen accumulation region 630 is disposed inthe combined oxide layer, such as at the second interface region 610between the oxidized nitride layer 510 a and the oxide layer 505. Thesecond interface region 610 is formed when a nitride layer is depositedon the oxide layer 505.

Accordingly, a number of free bonds may exist at the second interfaceregion 610 when the nitride layer was formed on the oxide layer 505. Inthis case, nitrogen atoms of the second nitrogen accumulation region 630may bond to the free bonds of the second interface region 610. At leastsome of the free bonds of the second interface region 610 may react witheach other or react to oxygen so as to be eliminated through a processperformed to fully oxidize the nitride layer. Because of the fulloxidation of the nitride layer, the second interface region 610 in thedielectric layer 515 may exist with an undefined shape, unlike someinterfaces between dissimilar materials. For example, the oxidizednitride layer 510 a is essentially formed of oxide so that the secondinterface region 610 between the oxidized nitride layer 510 a and theoxide layer 505 can appear to have a blended region therebetween,instead of a well defined interface therebetween.

The dielectric layer 515 can reduce/minimize free bonds between the gateelectrode 530 a and the substrate 500. Therefore, it may be possible toreduce/prevent charges stored in the charge storage layer 520 fromleaking through the free bonds. Moreover, it may be possible toreduce/prevent charges from being trapped by the free bonds during readoperations and/or program operations. As a result, data retentionproperties and/or durability of a non-volatile memory device may beenhanced.

A minimum field in the dielectric layer 515 can be stronger than that inthe blocking insulating layer 525. Thus, program operation speed and/orerase operation speed of a non-volatile memory device may be increasedwhile an operation voltage thereof may be decreased.

At least a portion of the gate electrode 530 a contacting the blockinginsulating layer 525 can have a high work function, which may decreasetunneling of charges migrating from the gate electrode 530 a to thecharge storage layer 520 through the blocking insulating layer 525. As aresult, erasing efficiency and/or programming efficiency of anon-volatile memory device may be enhanced.

While the present invention has been particularly shown and describedwith respect to exemplary embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A non-volatile memory device comprising: a dielectric layer includingan oxide layer on a substrate, the dielectric layer including at leasttwo regions therein that each extend across at least a major extent ofthe dielectric layer and have significantly higher nitrogenconcentration relative to other regions of the dielectric layer; acharge storage layer on the dielectric layer; a blocking insulatinglayer on the charge storage layer; and a gate electrode on the blockinginsulating layer.
 2. The non-volatile memory device as recited in claim1, wherein the at least two regions of the dielectric layer includes afirst region at an interface region between the oxide layer and thesubstrate and a second region in the oxide layer.
 3. The non-volatilememory device as recited in claim 2, wherein a nitrogen concentration ofthe first region is different from a nitrogen concentration of thesecond region.
 4. The non-volatile memory device as recited in claim 1,wherein the blocking insulating layer includes at least one insulatinglayer having a higher dielectric constant than a highest dielectricconstant portion of the dielectric layer.
 5. The non-volatile memorydevice as recited in claim 4, wherein the at least one insulating layerof the blocking insulating layer has a higher dielectric constant than ahighest dielectric constant of at least a major portion of thedielectric layer.
 6. The non-volatile memory device as recited in claim1, wherein the at least two regions of the dielectric layer havedifferent nitrogen concentrations.
 7. A method of forming a non-volatilememory device, the method comprising: forming a dielectric layerincluding a nitride layer on a substrate; transforming at least aportion of the nitride layer extending across at least a major lateralextent of the dielectric layer to include added oxygen; forming a chargestorage layer on the dielectric layer; forming a blocking insulatinglayer on the charge storage layer; and forming a gate electrode on theblocking insulating layer.
 8. The method as recited in claim 7, whereinthe transforming at least a portion of the nitride layer comprisesoxidizing the nitride layer.
 9. The method as recited in claim 8,wherein the nitride layer is partially oxidized.
 10. The method asrecited in claim 8, wherein the nitride layer is fully oxidized.
 11. Themethod as recited in claim 7, wherein the blocking insulating layer isformed to include at least one insulating layer having a higherdielectric constant than a highest dielectric constant portion of thedielectric layer.
 12. The method as recited in claim 11, wherein the atleast one insulating layer of the blocking insulating layer has a higherdielectric constant than a highest dielectric constant of at least amajor portion of the dielectric layer.
 13. A method of forming anon-volatile memory device, the method comprising: forming a dielectriclayer on a substrate; reacting at least a major portion of free bondsremaining in the dielectric layer to each other; forming a chargestorage layer on the dielectric layer; forming a blocking insulatinglayer on the charge storage layer; and forming a gate electrode on theblocking insulating layer.
 14. The method as recited in claim 13,wherein the reacting at least a major portion of the free bonds to eachother comprises oxidizing the dielectric layer.
 15. The method asrecited in claim 13, wherein the blocking insulating layer is formed toinclude at least one insulating layer having a higher dielectricconstant than a highest dielectric constant portion of the dielectriclayer.
 16. The method as recited in claim 15, wherein the least oneinsulating layer of the blocking insulating layer has a higherdielectric constant than a highest dielectric constant of at least amajor portion of the dielectric layer.
 17. A method of forming anon-volatile memory device, the method comprising: forming an oxidelayer on a substrate; forming a nitride layer on the oxide layer;oxidizing at least a portion of the nitride layer; forming a chargestorage layer on the oxidized nitride layer; forming a blockinginsulating layer on the charge storage layer; and forming a gateelectrode on the blocking insulating layer.
 18. The method as recited inclaim 17, wherein the nitride layer is partially oxidized.
 19. Themethod as recited in claim 17, wherein the nitride layer is fullyoxidized.